Holes and trench like patterns with a very high depth to width aspect ratio with micron or sub-micron openings have a number of applications in the manufacture of semiconductors. This description uses the term high aspect ratio holes to generically describe holes and trench like patterns that have a very high depth to width ratio of greater than 10 to 1. Various etching methods have been developed to generate such holes in silicon. The approaches use a lithographically defined mask pattern; wet chemical etch methods that take advantage of chemical selectivity along the crystal plane; and dry, plasma etch processes, which are done at low pressure to obtain a highly directional, anisotropic etch.
Very high aspect ratio holes have an application in semiconductor devices and in various miniature micro-machined devices (MIMMs). In semiconductor DRAM devices trenches for high capacitance structures with low surface area having aspect ratios of 50:1 and higher are being investigated for advanced designs. For both semiconductor and MIMMs devices, the need for subsequent patterning after making the very high aspect ratio holes usually requires a photolithographically defined mask pattern be made in a photosensitive polymer such as photoresist or photosensitive polyimide. In such a step, the high aspect ratio hole is filled with the photosensitive polymer.
Following the processes that use the polymer mask pattern, the polymer mask must be stripped from the device. In some applications, it may be advantageous to remove the polymer material partially, to a controlled depth to allow processing the upper, exposed section of the hole while the remaining polymer protects the lower section in the holes. A DRAM capacitor application that uses such a capability to increase the capacitor's area is described in “New Materials Enhance Memory Performance” a review by J. Baliga, Semiconductor International, November 1999, p 79-90, see p. 80.
Particularly for semiconductor applications, an additional requirement of the polymer removal process is that the exposed surface of the device not be subject to electrical degradation. Types of degradation that can occur in plasma removal processes may come from energetic species causing crystal damage or damage to a thin dielectric layer.
Standard methods of removing photo-polymers involve a method referred to as “ashing” in which a low pressure electrical discharge generates a plasma that creates chemically reactive oxygen species that flow to the surface to strip off the polymer and convert the polymer to volatile oxide by-products (e.g., HOx, COx). For very high aspect ratio holes, the flux of active oxygen species, that reaches the bottom of the hole, decreases as the aspect ratio increases, with the result that the etch rate of the polymer slows dramatically. One means to avoid this is to use a High Density Plasma (HDP). In this process, an intense plasma is generated at a low pressure. This pressure is sufficiently low so that the path length between collisions of plasma generated reactive species is sufficiently long so that reactive ions can be injected into the hole by acceleration of an electric field set-up in a boundary layer “sheath” over the surface of the substrate. A problem with this HDP approach is that the energetic ion species can electrically degrade the device's electrical characteristics.
The prior art has used the concept of a long path length between collisions with other gas species to enable a reactive species to reach the bottom of a very high aspect ratio hole where the species can convert the polymer to volatile by-products.